? semiconductor components industries, llc, 2008 october, 2008 ? rev. 6 1 publication order number: NCP5623/d NCP5623 triple output i2c controlled rgb led driver the NCP5623 mixed analog circuit is a triple output led driver dedicated to the rgb illumination or backlight lcd display. features ? 2.7 to 5.5 v input voltage range ? rgb function fully supported ? programmable integrated gradual dimming ? 90 ma total led current capability ? provides three independent led drives ? support i2c protocol ? this is a pb ? free device typical applications ? multicolor illuminations ? portable back light ? digital cellular phone camera photo flash ? lcd and key board simultaneous drive d1 c2 gnd c1 gnd sda r1 62 k gnd scl +vbat +vcc mcu i2c port vdet 12 iref 10 sda 9 scl 11 gnd 6 led3 3 led2 4 led1 5 u1 NCP5623 figure 1. typical multiple color led driver 1 f/6.3 v 1 f/6.3 v gnd vbat 13 gnd 2 ic nc nc ic 17814 +5 v 5 2 6 4 3 1 r g b lrtb ? g6t http://onsemi.com device package shipping ? ordering information ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. marking diagram 5623 = specific device code a = assembly location l = wafer lot y = year w = work week = pb ? free package NCP5623dtbr2g tssop ? 14 (pb ? free) 2500 / tape & reel 1 14 tssop ? 14 case 948g 5623 alyw 1 14 (note: microdot may be in either location)
NCP5623 http://onsemi.com 2 figure 2. pin assignments tssop ? 14 2 3 4 5 6 7 14 13 12 10 9 (top view ) led1 ic gnd led3 led2 gnd nc ic vbat iref sda vdet nc 11 scl 1 8 d1 d2 d3 c2 gnd gnd vbat c1 gnd sda r1 62 k gnd digital control pwm led#1 current NCP5623 vbat gnd scl pwm led#2 pwm led#3 functions gnd gnd gnd gnd led1 led2 led3 vbat figure 3. simplified block diagram analog 1 f/6.3 v 1.0 f/6.3 v mirrors 13 6 10 9 11 1 7 3 4 5 2 8 14 12 ic nc nc ic +5 v
NCP5623 http://onsemi.com 3 pin assignment pin name type description 1 ic this pin is internally connected. it must be left open. 2 gnd power this pin is the ground signal for the analog and digital blocks and output current control. the pin must be connected to the system ground, a ground plane being strongly recommended. 3 led3 output, power this pin sinks to ground and monitors the current flowing into the blue led, intended to be used in illumination application (note 1). the anode of the associated led shall be connected to the vbat supply. 4 led2 output, power this pin sinks to ground and monitors the current flowing into the green led, intended to be used in illumination application (note 1). the anode of the associated led shall be connected to the vbat supply. 5 led1 output, power this pin sinks to ground and monitors the current flowing into the red led, intended to be used in illumination application (note 1). the anode of the associated led shall be connected to the vbat supply. 6 gnd analog ground this pin copies the analog ground and shall be connected to the system ground plane. 7, 8 nc this pin must be left floating with no connection. 9 sda input, digital this pin carries the data provided by the i2c protocol. the content of the sda byte is used to program the mode of operation and to set up the output current. 10 i ref analog this pin provides the reference current, based on the internal band ? gap voltage reference, to control the output current flowing in the led. a 1% tolerance, or better, resistor shall be used to get the highest accuracy of the led current. an external current mirror can be used to bias this pin to dynamically set up the led maximum current. in no case shall the voltage at i ref pin be forced either higher or lower than the 600 mv provided by the internal reference. 11 scl input, digital this pin carries the i2c clock to control the i2c communication. the scl clock is associated with the sda signal. 12 vdet input this pin provides a dc bias to the internal circuit and must be connected to the same voltage that the one applied to the vbat pin 13. 13 vbat power this pin is the input battery voltage to supply the analog and digital blocks. the pin must be decoupled to ground by a 1 f or higher ceramic capacitor (note 2). 14 ic this pin is internally connected. it must be left open. 1. the maximum current is 37 ma for each led 2. using low esr ceramic capacitor, x5r type, is recommended.
NCP5623 http://onsemi.com 4 maximum ratings symbol rating value unit v bat power supply (see figure 4) ? 0.3 < v bat < 7.0 v sda, scl digital input voltage ? 0.3 < v < v bat v esd human body model: r = 1500 , c = 100 pf (note 3) machine model 2 200 kv v p d r jc r ja power dissipation @ t a = +85 c (note 4) thermal resistance junction to case thermal resistance junction to air 235 46 170 mw c/w c/w t a operating ambient temperature range ? 40 to +85 c t j operating junction temperature range ? 40 to +125 c t jmax maximum junction temperature +150 c t stg storage temperature range ? 65 to +150 c i latchup latch ? up current maximum rating per jedec standard: jesd78. 100 ma stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. moisture sensitivity level (msl): 1 per ipc/jedec standard: j ? std ? 020a. 3. this device series contains esd protection and exceeds the following tests: human body model (hbm) 2.0 kv per jedec standard: jesd22 ? a114 machine model (mm) 200 v per jedec standard: jesd22 ? a115 4. the maximum package power dissipation limit must not be exceeded. power supply section: (typical values are referenced to t a = +25 c, min & max values are referenced ? 40 c to +85 c ambient temperature, unless otherwise noted), operating conditions 2.85 v < v bat < 5.5 v, unless otherwise noted. pin symbol rating min typ max unit 13 v bat power supply 2.7 5.5 v 13 i stdb stand by current 3.0 v v bat 4.2 v, i led = 0 ma 0.8 1.0 a 13 i op operating current, @i led = 0 ma, 3.0 v v bat 4.2 v 350 a 3,4,5 i tol rgb output current tolerance @v bat = 3.6 v, i led = 10 ma ? 25 c < t a < 85 c 3 % 3,4,5 i match rgb output current led matching @v bat = 3.6 v, i led = 5.0 ma 0.5 % fpwr internal clock operating frequency ? 40 c < t a < 85 c 0.8 1 1.2 mhz
NCP5623 http://onsemi.com 5 analog section: (typical values are referenced to t a = +25 c, min & max values are referenced ? 40 c to +85 c ambient temperature, unless otherwise noted), operating conditions 2.85 v < v bat < 5.5 v, unless otherwise noted. pin symbol rating min typ max unit 10 i ref reference current @v ref = 600 mv (note 5, note 8) 3 12.5 20 a 10 v ref reference voltage (note 5) ? 3% 600 +3% mv i ledr reference current (i ref ) current ratio 2400 10 rbias external reference current bias resistor (note 6) 30 48 200 k 3,4,5 f pwm internal pwm frequency (note 7) 2.1 khz 5. the external circuit must not force the i ref pin voltage either higher or lower than the 600 mv specified. the system is optimized with a 12.5 a reference current. 6. the overall output current tolerance depends upon the accuracy of the external resistor. using 1% or better resistor is recom mended. 7. this parameter, derived from the 1 mhz clock, is guaranteed by design, not tested in production. digital parameters section: (typical values are referenced to t a = +25 c, min & max values are referenced ? 40 c to +85 c ambient temperature, unless otherwise noted), operating conditions 2.85 v < v bat < 5.5 v, unless otherwise noted. pin symbol rating min typ max unit 11 f scl input i2c clock frequency 400 khz 9,11 v ih positive going input high voltage threshold, sda, scl signals (note 8) 1.6 v bat v 9,11 v il negative going input low voltage threshold, sda, scl signals (note 8) 0 0.4 v note: digital inputs undershoot 0.30 v to ground, digital inputs overshoot < 0.30 v to v bat 8. test guaranteed by design and fully characterized, not implemented in production. 2.0 v 2.7 v 4.2 v 5.5 v 3.0 v power on reset normal li ? ion maximum voltage operation operation no operation during por 7.0 v absolute maximum rating chip functionnal, but no parameter guaranteed when vbat is between 5.5 v & 7.0 v the chip might be damaged or destroyed reserved for internal reset when vbat is above 7.0 v figure 4. understanding integrated circuit voltage limitations note: the internal por sequence is 850 s maximum long
NCP5623 http://onsemi.com 6 led maximum current calculation the load current is derived from the 600 mv reference voltage provided by the internal band gap associated to the external resistor connected across i ref pin and ground. note : due to the internal structure of this pin, no voltage, either downward or upward, shall be forced at the i ref pin. the reference current is multiplied by the constant k = 2400 to yield the output load current. since the reference voltage is based on a temperature compensated band gap, a tight tolerance resistor will provide a very accurate load current. the resistor is calculated from the ohm?s law (r bias = v ref /i ref ) and a more practical equation can be arranged to define the resistor value for a given maximum output current iledmax: r bias = (v ref *k)/iledmax [ 1 ] r bias = (0.6*2400)/iledmax r bias = 1440/iledmax [ 2 ] since the i ref to iledmax ratio is very high, it is strongly recommended to set up the reference current at 12.5 a to optimize the tolerance of the output current. although it is possible to use higher or lower value, as defined in the analog section, a 48 k / 1% resistor will provide the best compromise, the dimming being performed by the appropriate pwm registers. on the other hand, care must be observed to avoid leakage current flowing into either the i ref pin of the bias resistor network. finally, for any desired iled current, the curve provided figure 5 can be recalculated according to the equation: iled i ref k 31 n (eq. 1) iled v ref r bias 2400 31 n (eq. 2) with: n = step value @ 1 n 31 with: r bias = reference resistance with: k = internal multiplier constant = 2400 note: n=0 ? iled is set to zero n = 31 ? iled is set to the same current as n = 30 load connection the primary function of the NCP5623 is to control three led arranged in the rgb color structure (reference osram latb g66x). the brightness of each led is independently controlled by a set of dedicated pwm structure embedded into the silicon chip. the maximum current, identical for each led, is programmable by means of the i2c data byte. with 32 steps per pwm, the chip provides 32768 colors hue in a standard display. moreover, a built ? in gradual dimming provides a smooth brightness transition for any current level, in both upward and downward direction. the dimming function is controlled by the i2c interface: see table 2. the NCP5623 chip is capable to drive the three led simultaneously, as depicted in figure 1, but the load can be arranged to accommodate several led if necessary in the application. finally, the three current mirrors can be connected in parallel to drive a single powerful led, thus yielding 90 ma current capability in a single led. i2c protocol the NCP5623 is programmed by means of the standard i2c protocol controlled by an external mcu. the communication takes place with two serial bytes sharing the same i2c frame: ? byte#1 physical i2c address ? byte#2 selected internal registers & function b7 b6 b5 b4 b3 b2 b1 b0 byte#1 : i2c physical address, based 7 bits : % 011 1000 $38 * 0 1 1 1 0 0 0 r/w byte#2 : data register rled2 rled1 rled0 bled4 bled3 bled2 bled1 bled0 *note: according to the i2c specifications, the physical address is based on 7 bits out of the sda byte, the 8 th bit representing the r/w command. since the NCP5623 is a receiver only, the r/w command is 0 and the hexadecimal byte send by the mcu is %0111 0000 = $70
NCP5623 http://onsemi.com 7 b[7:5] : internal register selection: b7 b6 b5 function 0 0 0 chip shut down all led current = zero 0 0 1 set up the maximum output led current 0 1 0 pwm1 : red led control 0 1 1 pwm2 : green led control 1 0 0 pwm3 : blue led control 1 0 1 set the upward iend target 1 1 0 set the downward iend target 1 1 1 gradual dimming step time and run the contain of bits b[4:0] depends upon the type of function selected by bits b[7:5] as depicted in table 1 table 1. internal register bits assigment b7 b6 b5 b4 b3 b2 b1 b0 comments 0 0 0 x x x x x shut down 0 0 1 16 8 4 2 1 led current step, see figure 5 (note 9) 0 1 0 bpwm16 bpwm8 bpwm4 bpwm2 bpwm1 red pwm 0 1 1 bpwm16 bpwm8 bpwm4 bpwm2 bpwm1 green pwm 1 0 0 bpwm16 bpwm8 bpwm4 bpwm2 bpwm1 blue pwm 1 0 1 gdim5 16 gdim4 8 gdim3 4 gdim2 2 gdim1 1 set gradual dimming upward iend target (note 10) 1 1 0 gdim5 16 gdim4 8 gdim3 4 gdim2 2 gdim1 1 set gradual dimming downward iend target (note 10) 1 1 1 gdim5 128 ms gdim4 64 ms gdim3 32 ms gdim2 16 ms gdim1 8 ms gradual dimming time & run 9. the programmed current applies to the three led simultaneously, the gradual dimming is not engaged 10. the bit values represent the steps count, not the iled current: see equations 1 & 2, page 6, to derive the iled value. gradual dimming the purpose of that function is to gradually increase or decrease the brightness of the backlight led upon command from the external mcu. the function is activated and controlled by means of the i2c protocol. in order to avoid arithmetic division functions at silicon level, the period (either upward or downward) is equal to the time defined for each step, multiplied by the number of steps. to operate such a function, the mcu will provide two information: 1 ? the target current level (either upward or downward) 2 ? the time per step and run when a new gradual dimming sequence is requested, the output current increases, according to an exponential curve, from the existing start value to the end value. the end current value is defined by the contain of the upward or downward registers, the width of each step is defined by the time and run register, the number of step being in the 1 to 31 range. in the event of software error, the system checks that neither the maximum output current (30 ma), nor the zero level are forced out of their respective bounds. similarly, software errors shall not force the NCP5623 into an uncontrolled mode of operation. the dimming is built with 30 steps and the time delay encoded into the second byte of the i2c transaction: see table 1. when the gradual dimming is deactivated (b7 = b6 = 0, b5 = 1), the output current is straightforwardly set up to the level defined by the contain of the related register upon acknowledge of the output current byte. the gradual dimming sequence must be set up before a new output current data byte is send to the NCP5623 . at this point, the brightness sequence takes place when the new data byte is acknowledged by the internal i2c decoder. since the six registers are loaded on independent byte flow associated to the i2c address, any parameter of the NCP5623 chip can be updated ahead of the next function as depicted in t able 2.
NCP5623 http://onsemi.com 8 table 2. basic programming sequences i2c address command bits[7:0] operation note $70 000x xxxx system shut down bits[4:0] are irrelevant $70 0010 0000 0011 1111 set up the iled current iled register bits[4:0] contain the iled value as defined by the i ref value $70 0100 0000 0101 1111 set up the red pwm redpwm bits[4:0] contain the pwm value $70 0110 0000 0111 1111 set up the green pwm greenpwm bits[4:0] contain the pwm value $70 1000 0000 1001 1111 set up the blue pwm bluepwm bits[4:0] contain the pwm value $70 1010 0000 1011 1111 set up the iend upward upward bits[4:0] contain the iend value $70 1100 0000 1101 1111 set up the iend downward dwnwrd bits[4:0] contain the iend value $70 1110 0001 1111 1111 set up the gradual dimming time and run the sequence grad bits[4:0] contain the time value the number of step for a given sequence, depends upon the start and end output current range: since the iled value is encoded in the bits[4:0] binary scale, a maximum of 31 steps is achievable during a gradual dimming operation. the number of steps will be automatically recalculated by the chip according to the equation: nstep = | existing step position ? new step position | as an example, assuming the previously programmed step was 5 and the new one is 15, then we will have 10 steps to run between the actual location to the end value. if the timing was set at 16 ms, the total gradual dimming sequence will be 160 ms. to select the direction of the gradual dimming (either upward or downward), one shall send the appropriate register before to activate the sequence as depicted below: 1010 1111 1110 0011 select an upward sequence with 24 ms/step, the end iled current being (i ref *2400)/(31 ? 15) 1100 0001 1110 0100 select the downward sequence with 32 ms/step, the end iled current being (i ref *2400)/(31 ? 1). table 3. output current programmed value (iled = f(step)) step iled (ma) step iled (ma) step iled (ma) step iled (ma) 0 / $00 0 9 / $09 1.25 18 / $12 2.12 27 $1b 6.90 1 / $01 0.92 10 / $0a 1.31 19 / $13 2.30 28 / $1c 9.20 2 / $02 0.95 11 / $0b 1.38 20 / $14 2.50 29 / $1d 13.80 3 / $03 0.98 12 / $0c 1.45 21 / $15 2.76 30 / $1e 27.60 4 / $04 1.02 13 / $0d 1.53 22 / $16 3.06 31 / $1f 27.60 5 / $05 1.06 14 / $0e 1.62 23 / $17 3.45 6 / $06 1.10 15 / $0f 1.72 24 / $18 3.94 7 / $07 1.15 16 / $10 1.84 25 / $19 4.60 8 / $08 1.20 17 / $11 1.97 26 / $1a 5.52 note: the table assumes i ref = 11.5 a
NCP5623 http://onsemi.com 9 figure 5. output current programmed value ( iled = f(step) ) step 35 25 20 15 10 5 0 0 15 30 i led (ma) 30 10 25 5 20 pwm operation the built ? in pwm are fully independent and can be programmed to any value during the normal operation of the NCP5623 chip. the pwm operate with five bits, yielding a 32 steps range to cover the full modulation (0 to 100%) of the associated led: ? pwm = $00 the associated led is fully off, whatever be the programmed iled value ? pwm > $00 but < $1f the brightness of the associated led is set depending upon the pwm modulation value ? pwm = $1f the associated led is fully on, the current being the one defined by the iled value. each pwm is programmable, via the i2c port as depicted, at any time under any sequence arrangement as requested by the end system?s designer. the pwm does not change the iled value, but merely modulate the on/off ratio of the associated led. each step of the pwm represent 100/31 = 3.225% of the full range, the clock being 2.1 khz (typical). figure 6. basic rgb application d1 c2 gnd c1 gnd sda r1 62 k gnd scl +vbat +vcc mcu i2c port vdet 12 iref 10 sda 9 scl 11 gnd 6 led3 3 led2 4 led1 5 u1 NCP5623 1 f/6.3 v 1 f/6.3 v gnd vbat 13 gnd 2 ic nc nc ic 17814 +5 v 5 2 6 4 3 1 r g b lrtb ? g6t
NCP5623 http://onsemi.com 10 package dimensions tssop ? 14 case 948g ? 01 issue b dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l ? u ? seating plane 0.10 (0.004) ? t ? ??? ??? section n ? n detail e j j1 k k1 ? w ? 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t ? v ? 14x ref k n n 7.06 14x 0.36 14x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NCP5623/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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